This invention relates to a method for manufacturing dense, fine line printed circuit boards and multiple layer printed circuit board packages.
There are many methods of manufacturing printed circuit boards used extensively throughout the electronics industry. The advent of very large scale integrated circuits ("VLSI") has created an ever increasing demand for higher component density per unit of printed circuit board area. To meet this growing demand, printed circuit boards must be fabricated having extremely narrow conductor line widths and spacings. Because of the limitations inherent in the prior art methods, they cannot successfully meet the industry demands for high yield, multilayer printed circuit boards possessing good dimensional stability and ever-smaller line widths and spacings.
Although there are many methods known and used in the fabrication of printed circuit boards, the most widely accepted methods employ an etching technique. Typically, these methods include the steps of cladding a base of an electrically insulating material with a conductive copper foil, placing a photoresist material in intimate contact therewith, developing the photoresist material to define a conductive circuit pattern thereon, and etching away any exposed foil which is not covered with photoresist to provide a raised conductive circuit pattern.
This prior art method creates several problems since the conductor patterns are not flush with the surface of the circuit board, a conductor line can be easily scratched during handling, resulting in an open circuit Also, the copper conductor may sliver and bridge across adjacent conductors, causing short circuits.
Furthermore, the etching step in the prior art method may also create a variety of irregularities and defects in the printed circuitry. Etching may result in a conductor being overetched near its base, thereby undercutting the conductor causing a nonuniform, mushroom-shaped cross-section. Also, photoresist may become trapped beneath the mushroom ledges, preventing foil hidden beneath the trapped photoresist from being etched away. Over-etching, therefore, makes fine line stability and line width control extremely difficult to achieve as line and spacing widths and tolerances grow smaller. Thus, etching fabrication methods can result in multiple conductor line defects, significantly reducing board yields, with a consequent upsurge in rejected printed circuitry which increases final production costs.
Board flatness and dimensional stability are important characteristics for insuring that printed circuitry maintains continuous conductive interconnection with component leads and adjacent boards. However, temperature and pressure fluctuations that occur during lamination cause the board to warp creating considerable stresses to develop in printed circuitry mounted on equipment rails. These stresses cause conductors to break and/or to "swim" off the substrate fabricated by prior art methods because they have poor ductility and do not lay flush with the circuit board.
Quality and stability of multiple layer circuit board packages is also limited by prior art fabrication methods. To make such packages, lamination bonding layers of insulation must be sandwiched between circuit board layers to fill voids between the raised conductor lines and the circuit board substrate. Filling the voids requires high pressures during the lamination process which can destructively distort the conductor lines. Also, even very high pressures cannot insure that the laminate will fill all of the voids. Ultimately, many voids may remain within the finished multilayered package which become a depository of impurities. Such impurities can cause electrical shorts. Further, the lamination bonding layers and board substrates may be of different material composition since they are often supplied by different manufacturers, may be made of different resins, or come from different manufacturing runs. Consequently, the finished multilayer package is not homogeneous. Lack of homogeneity makes it difficult to set proper drill speeds, and drill angles in the fabrication of holes through the multilayers. In some cases the drill speed will be too fast to cut through the copper causing it to tear, but will be the proper speed to cut through the insulation. Thus, some of the layers will have tears, and others will be smooth and some will be extremely uneven, contributing to degraded board quality while increasing unit cost.
Achieving high density in printed circuitry also requires that a uniform, continuous conductive coating be placed on small diameter holes that are drilled through multilayer packages for component leads and interconnects. One technique widely known in the art for making hole walls conductive is electroless plating, whereby an electroless metal deposit, usually of copper, is uniformily coated on the dielectric board substrate. This technique has the disadvantage of depositing a coating that has poor adhesion qualities so that additional steps to insure adequate adhesion are required Another technique is the application of a thin electroless coating to the hole wall, then eletroplating to further build up the conductive surface. Conventional electroplating techniques, however, cannot access holes having small diameters and large depths demanded by fine line, high density printed circuitry. Therefore the prior art teaches coating very small diameter holes, such as 0.0115 or less totally by electroless processing which takes a substantial amount of processing time - 24 hours or more.